The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Semiconductor memory (memory) that stores binary data is generally of two types: volatile and nonvolatile. Volatile memory loses stored data when power to the memory is turned off. Nonvolatile memory, on the other hand, retains stored data even when power to the memory is turned off.
Memory is typically packaged in memory integrated circuits (ICs). Memory ICs comprise memory arrays. Memory arrays include rows and columns of memory cells (cells). Cells store binary data (bits). Cells of memory such as flash memory, phase-change memory, etc. can store more than one bit per cell.
Referring now to FIG. 1, an exemplary memory IC 10 is shown. The memory IC 10 comprises a memory array 12, a bit line decoder 14, a word line decoder 16, and a control module 18. The memory array 12 comprises (m+1)=M rows and (n+1)=N columns of (M*N) cells 20, where m and n are integers greater than 1. Each of the M rows includes N cells. The bit line decoder 14 selects N columns of cells 20 via bit lines BL0-BLn. The word line decoder 16 selects M rows of cells 20 via word lines WL0-WLm.
The control module 18 comprises a read/write (R/W) control module 22 and an address control module 24. The R/W control module 22 communicates with a host 26 via a bus 28. The bus 28 comprises address, data, and control lines. The host 26 issues R/W instructions to the R/W control module 22 via the bus 28 when reading and writing data from and to the cells 20. The RAN control module 22 reads and writes data from and to the cells 20 based on the R/W instructions. The address control module 24 controls addressing of the cells 20 via the bit line decoder 14 and the word line decoder 16 during R/W operations.